1. Field of the Invention
The present invention relates to a synchronous semiconductor device such as a synchronous complementary metal oxide semiconductor (CMOS) memory device.
2. Description of the Related Art
Recently, in a semiconductor device, in order to reduce a large skew due to the fluctuation of input and output signals, synchronous semiconductor devices have been used.
In a prior art synchronous semiconductor memory device input signals of an emitter-couped logic (ECL) level are held at ECL input latch circuits clocked by an ECL level clock signal, and are supplied to an ECL memory circuit. Output signals of the ECL memory circuit are held at ECL output latch circuits clocked by the ECL level clock signal and are output therefrom. In this prior art ECL memory device, since the ECL level input signals and the ECL level clock signal have a small amplitude such as 0.4 V, the operation speed is large and a skew, i.e., a difference among the input signals or among the output signals is small. This will be later explained in detail.
In the above-mentioned prior art ECL semiconductor memory device, however, since the ECL latch circuits formed by bipolar transistors require a large DC current, one half or one third of the entire power is consumed in the ECL latch circuits. Also, the layout patterns of the ECL latch circuits are large, so the integration of the device is reduced.
In another prior art synchronous semiconductor memory device, input signals of an ECL level are converted into input signals of a CMOS logic level. Then, the CMOS logic level input signals are held at CMOS input latch circuits clocked by a CMOS logic level clock signal, and are supplied to a CMOS memory circuit. Output signals of the CMOS memory circuit are held at CMOS output latch circuits clocked by the CMOS logic level clock signal and are output therefrom. In this prior art CMOS memory device, since the input and output CMOS latch circuits require no DC current, the power consumption can be reduced. Also, since the layout patterns of the CMOS latch circuits are relatively small, the integration of the device is improved (see: JP-A-61-227285). This will be explained later in detail.
In the above-mentioned prior art CMOS synchronous semiconductor memory device, however, since the CMOS logic level clock signals which have a large amplitude such as 2.5 V are supplied via long paths to the input CMOS latch circuits, a large difference in operation speed generated among the input CMOS latch circuits, i.e., a large skew, is generated, so that the set timing and holding characteristics of the CMOS input signals are deteriorated. Also, since the propagation speed of the CMOS logic level signal having a large amplitude on the long paths is low, the operation speed of the device is also reduced.